System-Level Design Techniques for Energy-Efficient Embedded Systems addresses the development and validation of co-synthesis techniques that allow an effective design of embedded systems with low energy dissipation. The book provides an overview of a system-level co-design flow, illustrating through examples how system performance is influenced at various steps of the flow including allocation, mapping, and scheduling. The book places special emphasis upon system-level co-synthesis techniques for architectures that contain voltage scalable processors, which can dynamically trade off between computational performance and power consumption. Throughout the book, the introduced co-synthesis techniques, which target both single-mode systems and emerging multi-mode applications, are applied to numerous benchmarks and real-life examples including a realistic smart phone.
Table of ContentList of Figures. List of Tables. Preface. Acknowledgements. 1: Introduction. 1.1. Embedded System Design Flow. 1.2. System Specification. 1.3. Co-Synthesis. 1.4. Hardware and Software Synthesis. 1.5. Book Overview. 2: Background. 2.1. Energy Dissipation of Processing Elements. 2.2. Energy Minimisation Techniques. 2.3. Energy Dissipation of Communication Links. 2.4. Further Reading. 2.5. Concluding Remarks. 3: Power Variation-Driven Dynamic Voltage Scaling. 3.1. Motivation. 3.2. Algorithms for Dynamic Voltage Scaling. 3.3. Experimental Results: Energy-Gradient-Based Dynamic Voltage Scaling. 3.4. Concluding Remarks. 4: Optimisation of Mapping and Scheduling for Dynamic Voltage Scaling. 4.1. Schedule Optimisation. 4.2. Optimisation of Task and Communication Mapping. 4.3. Optimisation of Allocation. 4.4. Concluding Remarks. 5: Energy-Efficient Multi-Mode Embedded Systems. 5.1. Preliminaries. 5.2. Motivational Examples. 5.3. Previous Work. 5.4. Problem Formulation. 5.5. Co-Synthesis of Energy-Efficient Multi-Mode Systems. 5.6. Experimental Results: Multi-Mode. 5.7. Concluding Remarks. 6: Dynamic Voltage Scaling for Control Flow-Intensive Applications; Dong Wu, B.M. Al-Hashimi, P. Eles. 6.1. The Conditional Task Graph Model. 6.2. Schedule Table for CTGs. 6.3. Dynamic Voltage Scaling for CTGs. 6.4. Voltage Scaling Technique for CTGs. 6.5. Conclusions. 7: LOPOCOS: A Low Power Co-Synthesis Tool. 7.1. Smart Phone Description. 7.2. LOPOCOS. 7.3. Concluding Remarks. 8: Conclusion. 8.1. Summary. 8.2. Future Directions. References. Index.
Language English ● Format PDF ● Pages 194 ● ISBN 9780306487361 ● File size 11.6 MB ● Age 02-99 years ● Publisher Springer US ● City NY ● Country US ● Published 2006 ● Downloadable 24 months ● Currency EUR ● ID 2143687 ● Copy protection Adobe DRM
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