Chris Spear 
SystemVerilog for Verification 
A Guide to Learning the Testbench Language Features

System Verilog for Verification provides practical information for hardware and software engineers using the System Verilog language to verify electronic designs. The authors explain methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the System Verilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. It also reviews System Verilog 3.0 topics such as interfaces and data types.

For hardware engineers, the book has several chapters with detailed explanations of Object Oriented Programming based on years of teaching OOP to hundreds of students. For software engineers, there is a wealth of information on testbenches, multithreaded code, and interfacing to hardware designs. The reader only needs to know the Verilog 1995 standard.

Innehållsförteckning