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James E. Morris 
Nanopackaging 
Nanotechnologies and Electronics Packaging

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Copertina di James E. Morris: Nanopackaging (PDF)

Nanotechnologies are being applied to microelectronics packaging, primarily in the applications of nanoparticle nanocomposites, or in the exploitation of the superior mechanical, electrical, or thermal properties of carbon nanotubes. Composite materials are studied for high-k dielectrics, resistors and inductors, electrically conductive adhesives, conductive “inks, ” underfill fillers, and solder enhancement. “Nanopackaging” is intended for industrial and academic researchers, industrial electronics packaging engineers who need to keep abreast of their field, and others with interests in nanotechnology. It will survey the application of nanotechnologies to electronics packaging, as represented by current research across the field.

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Nanopackaging: Nanotechnologies and Electronics Packaging.- Modelling Technologies and Applications.- Application of Molecular Dynamics Simulation in Electronic Packaging.- Advances in Delamination Modeling.- Nanoparticle Properties.- Nanoparticle Fabrication.- Nanoparticle-Based High-k Dielectric Composites: Opportunities and Challenges.- Nanostructured Resistor Materials.- Nanogranular Magnetic Core Inductors: Design, Fabrication, and Packaging.- Nanoconductive Adhesives.- Nanoparticles in Microvias.- Materials and Technology for Conductive Microstructures.- A Study of Nanoparticles in Sn Ag-Based Lead-Free Solders.- Nano-Underfills for Fine-Pitch Electronics.- Carbon Nanotubes: Synthesis and Characterization.- Characteristics of Carbon Nanotubes for Nanoelectronic Device Applications.- Carbon Nanotubes for Thermal Management of Microsystems.- Electromagnetic Shielding of Transceiver Packaging Using Multiwall Carbon Nanotubes.- Properties of 63Sn-37Pb and Sn-3.8Ag-0.7Cu Solders Reinforced With Single-Wall Carbon Nanotubes.- Nanowires in Electronics Packaging.- Design and Development of Stress-Engineered Compliant Interconnect for Microelectronic Packaging.- Flip Chip Packaging for Nanoscale Silicon Logic Devices: Challenges and Opportunities.- Nanoelectronics Landscape: Application, Technology, and Economy.- Errata.
Lingua Inglese ● Formato PDF ● Pagine 543 ● ISBN 9780387473260 ● Dimensione 14.4 MB ● Editore James E. Morris ● Casa editrice Springer US ● Città NY ● Pubblicato 2008 ● Scaricabile 24 mesi ● Moneta EUR ● ID 2145200 ● Protezione dalla copia Adobe DRM
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